An integrated circuit (“IC”) is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.
Design engineers design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. IC design layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins, and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC.
To create the design layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts.
Fabrication foundries (“fabs”) manufacture ICs based on the design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., photomask) are imaged and defined onto a photosensitive layer coating a substrate. To fabricate an IC, photomasks are created using the IC design layout as a template. The photomasks contain the various geometries (i.e., features) of the IC design layout. The various geometries contained on the photomasks correspond to the various base physical IC elements that comprise functional circuit components such as transistors, interconnect wiring, via pads, as well as other elements that are not functional circuit elements but that are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.
As circuit complexity continues to increase and transistor designs become more advanced and ever smaller in size (i.e., die shrink), advances in photolithographic processes are being pursued to enable the large scale, low cost manufacturing of such circuits. However, constraining factors in traditional photolithographic processes limit the effectiveness of current photolithographic processes. Some such constraining factors are the lights/optics used within the photolithographic processing systems. Specifically, the lights/optics are band limited due to physical limitations (e.g., wavelength and aperture) of the photolithographic process. Therefore, the photolithographic process cannot print beyond a certain pitch, distance, and other such physical manufacturing constraints.
A pitch specifies a sum of the width of a feature and the space on one side of the feature separating that feature from a neighboring feature. Depending on the photolithographic process at issue, factors such as optics and wavelengths of light or radiation restrict how small the pitch may be made before features can no longer be reliably printed to a wafer or mask. As such, the smallest size of any features that can be created on a wafer is severely limited by the pitch.
FIG. 1 illustrates a typical pitch constraint of a photolithographic process. In FIG. 1, a pitch 110 acts to constrain the spacing between printable features 120 and 130 of a design layout. While other photolithographic process factors such as the threshold 140 can be used to narrow the width 150 of the features 120 and 130, such adjustments do not result in increased feature density without adjustments to the pitch 110. As a result, increasing feature densities beyond a certain threshold is infeasible via a pitch constrained single exposure process.
Certain reticle enhancement techniques (RET) allow for photolithographic processes to extend beyond some of the various photolithographic manufacturing constraints such as the width constraint. Some common techniques include: using optical proximity correction (OPC) to distort photomask shapes to compensate for image errors resulting from diffraction or process effects that cause pattern inaccuracies, using off-axis illumination (OAI) for optimizing the angle of illumination for a particular pitch, using alternating phase shift masks (PSM) for improving lithographic resolution by introducing a particular phase shift between adjacent patterns or features on a photomask, and using scatter bars to place narrow lines or spaces adjacent to a feature in order to make a relatively isolated line behave more like a dense line.
However, these and other techniques are limited both by cost and effectiveness. To overcome these and other constraints, some fabrication processes have implemented a multiple exposure photolithographic process as illustrated in FIG. 2.
In FIG. 2, a design layout 205 specifies three features 210-230 that are pitch constrained and therefore cannot be photolithographically printed with a conventional single exposure process. Analysis of the characteristics (e.g., the band limitation) of the available photolithographic process and of the design layout 205 results in the decomposition of the design layout 205 into a first exposure 240 for printing features 210 and 230 and a second exposure 250 for printing feature 220. As such, the features 210 and 230 are assigned to a first photomask for printing during the first exposure 240 and feature 220 is assigned to a second photomask for printing during the second exposure 250.
FIG. 3 illustrates a decomposition of a pattern 310 defined in a layer of design layout for fabricating an IC into two sets of polygons 320 and 330. Each such decomposed set of polygons 320 and 330 is printed during an exposure of a multiple exposure photolithographic printing process. For instance, polygon set 320 is printed during a first exposure in order to produce contours 340 and polygon set 330 is printed during a second exposure in order to produce contours 350. The resulting union of the contours 340 and 350 generates pattern 360 that is sufficient to approximately reproduce the original pattern 310. Accordingly, a valid decomposition solution is such that the union of the contours created/printed from each exposure closely approximates specifications within the original design layout and satisfies multi-exposure photolithographic printing constraints (e.g., the band limit and the target layout specified within the design layout) with no resulting “opens”, “shorts”, or other printing errors materializing on the physical wafer.
Existing decomposition tools for decomposing layouts into one or more exposures are often rule based and proceed on a pattern by pattern (i.e., geometry by geometry) basis. Such tools are therefore applicable only to patterns for which a pre-programmed or known decomposition solution exists within a library. These tools are effective for decomposing simple designs with regular repeating patterns such as gradings including lines and spaces. However, design layouts with more sophisticated geometries (e.g., logic designs and microprocessor designs containing complex patterns and shapes with bends and jogs) cannot be processed using these existing decomposition tools as solutions do not exist for the unique patterns appearing within such design layouts. Instead, layout designers would be notified of the patterns for which a known solution does not exist. The layout designers would then be prompted to manually produce a decomposition solution for these patterns. To remedy this issue, solution providers must continually update the pattern libraries and algorithms used by these tools to accommodate the growing complexity of the design layouts.
Moreover, existing decomposition tools are inefficient in the manner by which they perform decomposition analysis. Repeated polygonal patterns within a single design layout are each independently analyzed and a solution is provided for each instance as if each instance is the first such instance. Therefore, the more dense a design layout, the more time and processing resources needed to process and decompose the design layout. Also, traditional prior art decomposition tools often operate in a local area by local area basis such that solutions provided to remedy printability issues appearing within a particular local area may have a detrimental effect to other unprocessed or processed local areas of the layout.
Therefore, there is a need to efficiently and effectively decompose an entire layout or section of a layout while avoiding the pitfalls associated with geometric rule based decomposition techniques. Moreover, there is need to generalize such techniques and tools such that the applicability of these techniques and tools is no longer restricted to a known or pre-programmed set of solutions.